1. Field
The present disclosure relates to network processor. More particularly, this invention is directed toward arbitrating work request from a plurality of requestors in a network processor.
2. Description of Related Technology
A network processor is specialized processor, often implemented in a form of an integrated circuit, with a feature set specifically designed for processing packet data received or transferred over a network. Such packet data is transferred using a protocol designed, e.g., in accordance with an Open System Interconnection (OSI) reference model. The OSI defines seven network protocol layers (L1-7). The physical layer (L1) represents the actual interface, electrical and physical that connects a device to a transmission medium. The data link layer (L2) performs data framing. The network layer (L3) formats the data into packets. The transport layer (L4) handles end to end transport. The session layer (L5) manages communications between devices, for example, whether communication is half-duplex or full-duplex. The presentation layer (L6) manages data formatting and presentation, for example, syntax, control codes, special graphics and character sets. The application layer (L7) permits communication between users, e.g., by file transfer, electronic mail, and other communication known to a person of ordinary skills in the art.
The network processor may schedule and queue work, i.e., packet processing operations, for upper level network protocols, for example L4-L7, and being specialized for computing intensive tasks, e.g., computing a checksum over an entire payload in the packet, managing TCP segment buffers, and maintain multiple timers at all times on a per connection basis, allows processing of upper level network protocols in received packets to be performed to forward packets at wire-speed. Wire-speed is the rate of data transfer of the network over which data is transmitted and received. By processing the protocols to forward the packets at wire-speed, the network services processor does not slow down the network data transfer rate. An example of such processor may be found in U.S. Pat. No. 7,895,431.
To improve network processor efficiency, multiple cores are scheduled to carry the processing via a scheduling module. The scheduling module divides the work to be scheduled into a plurality of (ideally) parallel streams, called groups. However, having a large number of such groups means there may be a large number of parallel requests for work from the multiple cores, which need to be arbitrated. Arbitration is a process of selecting work from the plurality of groups to be returned to the requestor. Arbitration solutions known in the art are either expensive in area required on the network processor chip, expensive in time it takes to process the request, or do not allow for different weighting or selecting what groups participate in the arbitration.
Accordingly, there is a need in the art for method and an apparatus providing a solution to the above identified problems, as well as additional advantages.